What causes receiver input clock cycle-to-cycle jitter?
Any jitter from the transmitter output clock will be passed to the receiver input clock. As a result, it is important to keep the transmitter output clock cycle-to-cycle jitter (TJCC) to a minimum. Possible sources of noise that can increase transmitter output cycle-to-cycle jitter include power supply noise, and cycle-to-cycle jitter from oscillators, FPGAs or other clock sources used at the transmitter input.
