What are the steps needed to process a maskable interrupt in C6000?
Please see Setting up interrupts in DSP BIOS for a detailed description. From the hardware perspective the following steps should be taken care for a maskable interrupt to be processed: • The peripheral must be configured properly to generate an interrupt. • The interrupt source must be mapped to one of the 12 maskable CPU interrupts through the INTMUX registers (MUXL/MUXH on devices prior to 64x+). • The corresponding interrupt enable (IE) bit in the IER should be set to one. • The non-maskable interrupt enable bit (NMIE) bit in the interrupt enable register (IER) should be set to one. Note: once NMIE is set to one it cannot be cleared except by an NMI or reset. • The global interrupt enable bit (GIE) bit in the control status register (CSR) should be set to one. When the interrupt occurs, the corresponding bit in the IFR will be set to one. The interrupt will be serviced if there are no higher priority interrupt flag (IF) bits set in the IFR. The CPU automatically clears the correspo
