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What are the steps for enabling the ECC feature in CPC710-133?

April 26, 2017ECC enabling feature steps

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What are the steps for enabling the ECC feature in CPC710-133?

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To run ECC correctly it is necessary that all Data stored in SDRAM memory is coherent with ECC: Check bits have to be set such that it is in agreement with the data. During init phase some data may not be coherent with ECC and setting must disable ECC, up to a point where all Data stored in SDRAM memory is coherent. This can be done with a Write all Zero in memory for example, before turning “on” the ECC mode.