What are the specific benefits of the Tela Layout Optimization solution, in terms leakage, performance, design time, etc?
The key benefits of the Tela solution are a reduction in die area and a reduction in variability resulting in improved performance and lower leakage. Area reduction is achieved though a combination of Telas proprietary layout techniques and in optimizing the process technology for the fixed, regular nature of Telas implementation. With relatively minor optimization we are seeing approximately 20% smaller logic block areas. These results are post timing driven place and route results using actual customer netlists with comparable route utilization rates. In terms of variability reduction Tela provides two benefits, first reducing device level variability buy improving the uniformity of the gate length critical dimension (CD) across the width of the transistor. This is due to the straight line nature of Telas architecture. A second benefit is in further variation reduction incontext dependant variation which arises from the surrounding lithographic neighborhood in which a device is place
