What are the native design checks provided in Discovery?
For many years, increasingly sophisticated static and dynamic checks have been available for digital designs in RTL. Static checks, such as those provided by Leda, VCS and MVRC, catch many design bugs quickly, without simulation or significant extra effort for the designer. With VCS, users can perform dynamic checks, using custom SystemVerilog assertions or VCS Assertion IP. Verifying complex mixed-signal designs with sophisticated digitally controlled analog functions, multiple supply domains, and thousands of interface signals between the digital and analog blocks accurately is a major challenge. The traditional approach of using dynamic simulation alone may not be enough to ensure adequate coverage of the chip’s intended operations. CustomSim provides a comprehensive circuit simulation solution that includes static and dynamic native circuit checking to rapidly identify electrical rule violations and power management failures, thereby increasing designer productivity and confidence.
Related Questions
- Can I design full-working engines not originally provided with Net Yaroze, or am I limited to use the engines provided when I join?
- What type of support will be provided for the design and creation of printed and video informational materials?
- The materials from The Discovery Institute were not provided directly to the board, correct?
