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What are the major differences between clock generator (CG) and deskew (DS) PLL designs?

April 26, 2017CG clock Designs deskew differences DS generator PLL

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What are the major differences between clock generator (CG) and deskew (DS) PLL designs?

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Compared to CG PLLs, DS PLLs need to run at higher bandwidths to control input-to-output jitter. This bandwidth constraint limits the amount of frequency multiplication that can be done. Also, achieving low static phase offset imposes other constraints that narrow the multiplication range. CG PLLs can use lower bandwidths and allow wider multiplication ranges.