What are the improvements to the Reset Circuit of the new Neuron 3120s?
The external reset signal is synchronized internally with the Neuron Chip system clock. All resets (LVD, Watchdog, Software and external) are now synchronized, improving EEPROM reliability. The reset signal can be asserted for either 3 clock cycles (same as earlier Neurons), or minimum 50 msec. This feature is controlled by bit 0 of I/O address 0xFFF5 as follows: 0 = 50 msec (default), 1 = 3 cycles. After a power-on reset, this control bit is cleared, setting the reset time to the default value of 50 msec. If you would like to use the shorter (3 cycle) reset time in your application, you should set the control bit in its reset processing task.
