What advantages does National Semiconductor BLVDS have over LVDS I/O integrated into the latest FPGA\s?
Discrete BLVDS devices use a standard 3.3V supply level. Often times LVDS I/O on an FPGA will require a 2.5V supply level. The additional regulation and board space consumed more than offsets the area and power consumed with a 3.3V discrete solution. The pinout used for discrete LVDS products offers easy routing to all popular connector styles. The ability to cleanly route signals to and from a connector allows the discrete LVDS devices to be placed in close proximity to connectors or other ICs. Placing discrete transceivers close to the connector dramatically improves the signal integrity of the backplane interface. Bus LVDS devices often tout ESD performance well in excess of 4Kv. This robust ESD performance enhances the reliability of any system. FPGAs that do not have true complimentary outputs require attenuation networks to achieve LVDS like switching levels. This solution requires two LVCMOS FPGA outputs to drive the attenuation network doubling the internal dynamic power of the
