Went from Xilinx to Altera: Cyclone-II and I/O pullup?
120783: 07/06/16: Re: Using LogicLock in Altera Quartus II 121930: 07/07/15: Re: What is the resistance of a big FPGA for VCCINT (unpowered) 121932: 07/07/15: Re: ESR Meter – design contest 121946: 07/07/16: Re: QuartusII Web Edition software question 122395: 07/07/26: Re: Question about Bottom-Up Incremental Compilation Methodology in Quartus II 122587