The standard does not explicity specify the nature of the input ramp in obtaining ramp rates. What should be the input rise time as well as the high and low values of the input pulse?
IBIS does not provide an Input pulse specification for deriving Ramp rates (and Waveform Tables). A reasonable guideline is to mimic actual conditions for which the device would be used. Therefore it is probably better not to mandate a specific condition. The voltage swing should be appropriate for the technology, e.g., 0 to 5V for CMOS and about 0 to 3V for TTL. A signal faster than the expected Ramp rates is my preference, although a case could be made to provide a response that mimics the data book input ramps specified for timing tests. Possibly a 50 Ohm series resistance approximating the pulser source impedance and trace environment to the device input should be included. However, since the actual thresholds are narrow (several 100 mV), the Ramp rates and Waveform tables should not differ significantly for any reasonable, appropriate Input.
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