The older S100 boards only had 16 bit addressing. While I don expect to put them in banks, what problems will there be?
(h) Many old S-100 boards only decode 16-bits of addressing. This will cause a problem if you want to run an old board that uses memory mapped I/O or contains its own RAM or ROM. There is a solution for this where you can punch “holes” in the address space in the lower 64K for these boards and then only generate the MWRT and sMEMR signals on the bus for CPU-generated addresses that are in the lower 64K. This is possible by reprogramming the Lattice CPLD which does all of the glue/decode logic on the MPU-C. This is not trivial; however, I may make some example CPLD code that shows how to do this. I will definitely do it myself, because I want to use a Northstar MDS floppy controller with the system, and this card uses memory mapped I/O from E800h-EBFFh. Another solution is to add some decoding logic to each adapter board that decodes the upper 4-bits. This may be the most versatile solution, as you can then keep “Bank 0” as a solid 64K RAM bank, and locate your controllers in some of th
