The host processor I’m using doesn’t have a DTACK* or READY input. Can I still use the DD-42900?
A. Yes. It is important to note that write cycles do not require the DTACK* or READY handshake signals at all because both the data and address information from the processor are latched internally to the DD-42900 upon the rising edge of the write signal, even if the DD-42900 is not immediately ready to write the data to its final destination. It is also important to note that DTACK* and READY are only required on read cycles from Data Store RAM or Data Match RAM. These are denoted as Type 3 Reads on the DD-42900 data sheet and may take several clock cycles longer than a Type 1 or 2 read. This is because the RAM is shared between the host processor and the internal DD-42900 processors.
