The decision was made to prevent clock manipulation to guarantee synchronous design. Why?
• All EDA tools are optimized for synchronous logic. • Asynchronous logic is a great way to introduce bugs. With Confluence, you can still design multirate systems, but you must use multiple enables, not multiple clocks. For designs with asynchronous clock domains, there is an example in the library (sync.cf) that explains how safely move data across two asynchronous clock domains.
