Slice Virtex II = Equivalent gates ??
84369: 05/05/17: Re: Registers replication on Xilinx IOBs 84387: 05/05/18: Re: VHDL array question 84428: 05/05/18: Re: VHDL array question 84435: 05/05/18: Re: How many logic cells are there in one slice 84451: 05/05/19: Re: How many logic cells are there in one slice 84603: 05/05/22: Re: Virtex4 Block Ram : ISE6.3 Problem 84661: 05/05/24: Re: re:FSM stops working 84663: 05/05/24: Re: Nondeterministic ISE Placement 84664: 05/05/24: Re: Xilinx Answer Record 21127 84866: 05/05/31: Re: Timing summary 85148: 05/06/06: Re: Magical Mystery Tour of ISE environment variables 85549: 05/06/10: Re: floorplanning 85555: 05/06/10: Re: computer upgrade time. 85572: 05/06/10: Re: computer upgrade time.