Performance of Xilinx System Generator RTL?
75964: 04/11/20: Re: Custom Megafunctions in Quartus II 75979: 04/11/21: Re: 18×18 Multipliers – Spartan III 75980: 04/11/21: Re: Custom Megafunctions in Quartus II 76028: 04/11/22: Re: Async and sync resets 76082: 04/11/23: Re: Choice of FPGA device 76166: 04/11/27: Re: Choice of FPGA device — my view on benchmarks 76172: 04/11/27: Re: dual-write port BRAM with XST/Webpack 76183: 04/11/27: Re: dual-write port BRAM with XST/Webpack 76193: 04/11/28: Re: dual-write port BRAM with XST/Webpack 76194: 04/11/28: Re: dual-write port BRAM with XST/Webpack 76195: 04/11/28: Re: Choice of FPGA device — my view on benchmarks 76201: 04/11/28: Re: dual-write port BRAM with XST/Webpack 76309: 04/11/30: Re: Verilog newbie with clocking question 76385: 04/12/01: Re: Weird XPower results for FSMs and different FPGAs 76495: 04/12/04: Re: how to start with development of eda tools 76520