OpenCores tracker and forum doesn work?
132306: 08/05/21: Re: timing constraint is impossible to meet 133575: 08/07/04: Re: Spartan3: INIT_B doesn’t go LOW after PROG_B goes LOW in 2% of 136951: 08/12/15: Synthesizable & open 4DDR Infiniband core 136966: 08/12/16: Re: Synthesizable & open 4DDR Infiniband core 140539: 09/05/16: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python without 140541: 09/05/16: Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python without 140559: 09/05/17: Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python without 140560: 09/05/17: Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python without 140739: 09/05/23: Re: BSCAN_SPARTAN3 proper use with CAPTURE and UPDATE 143573: 09/10/16: Controller to access internal FPGA registers from JTAG 143691: 09/10/21: Xilinx USB programmer – problems with Debian/Linux – Solved 144702: 09/12/25: VHDL: assignment to two different fields of the record in two 144703: 09/12/25: More details: VHDL: assignment to two different fields of the 149253: 10/10/
