On the AD9510, what is the relationship between clock output jitter and CLK1/CLK2 input slew rate?
The higher the slew rate at the CLK1/CLK2 inputs, the lower the jitter, in general. This is because the input signal transitions through the decision point more quickly and therefore is less subject to disturbance by noise. The datasheet specs require a minimum of 1 V/ns slew rate at these inputs.
