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On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window?

AD9510 clocks CYCLE duty output sure
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On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window?

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A divide-by-3 will produce a duty cycle of 33.3%-66.6%. A divide-by-5 produces exactly 40%-60%. Higher odd divide ratios (7, 9, 11…) produce duty cycles within the 40%-60% window.

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