New IP with EDK : how connect external NET ?
110583: 06/10/18: jbnote: from LUT contents to boolean equation 110584: 06/10/18: Markus: Re: from LUT contents to boolean equation 110589: 06/10/18: Ray Andraka: Re: from LUT contents to boolean equation 110588: 06/10/18: jbnote: Re: from LUT contents to boolean equation 110585: 06/10/18: Mak: EDIF netlist timing simulation 110587: 06/10/18: Mak: Re: EDIF netlist timing simulation 110608: 06/10/18: Petter Gustad: Re: EDIF netlist timing simulation 110593: 06/10/18: Petter Gustad: Re: EDIF netlist timing simulation 110594: 06/10/18: samiam: Cheapest FPGA board to study VHDL on 110598: 06/10/18: John Adair: Re: Cheapest FPGA board to study VHDL on 110602: 06/10/18: samiam: Re: Cheapest FPGA board to study VHDL on 110601: 06/10/18: Mike Treseler: Re: Cheapest FPGA board to study VHDL on 110603: 06/10/18: samiam: Re: Cheapest FPGA board to study VHDL on 110669: 06/10/19: Mike Treseler: Re: Cheapest FPGA board to study VHDL on 110640: 06/10/19: Paul Burke: Re: Cheapest FPGA board to study