My “always” statement doesn trigger at time 0. Is Icarus Verilog broken?
In this case, the bug is most likely in your program, and is probably the most common and unnoticed error in the entire history of Verilog use. Your program probably looks something like this: reg [7:0] a, b, c; always @(a or b) c = a + b; initial begin a = 1; b = 2; end This is in fact a race condition at time zero. James Lee has this to say: [T]he bug is the race between the always at time zero getting to the @ and the initial setting the values. A #1 in the initial block before changing a or b should do the trick. I think that most verilog simulators have some sort of trick to catch the changes at time zero. The IEEE 1364-1995 standard is also clear on this issue: the given example leaves c with an unpredictable value at time 0. This is a frightfully common mistake, we’ve all done it. It often goes unnoticed because compilers often start threads from first (in the source file) to last. It just so happens that Icarus Verilog, by a detail of implementation, starts threads from last to
