modularity” — is that just that they didn do the whole SPART in one big verilog source file?
You can see whether thier functional blocks makes sense or not. I believe they just followed the diagram. 2.25 – “module interface” — I’m not sure what you’re looking for with this one… This one deals with the declaration of each module. They should have some kind of convention to start with input or output fisrt but not mixed. The second issue is about moule instantiation. They should use the dot notation. Another one is about naming of the input/output ports whether they are meaningful or not.
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- modularity" -- is that just that they didn do the whole SPART in one big verilog source file?
