LVDCI for inputs?
132059: 08/05/12: value of the weak pull up resistor on IOBs of Virtex5 132427: 08/05/27: Re: signal value at power up 133578: 08/07/04: Single ended interface at 70Mhz for FPGAs 133622: 08/07/06: Re: Single ended interface at 70Mhz for FPGAs 133627: 08/07/07: Re: Serial Pheripheral Interface for XILINX FPGA 133791: 08/07/15: Re: Xilinx tools in Windows or Linux – Suggestions 134215