Keep Xilinx Webpack from removing unused NETs?
34073: 01/08/13: Re: Fast Mux and low power voltage reference 34074: 01/08/13: Re: virtex2 Block Ram: dual port ram with different da 34076: 01/08/13: Re: Slightly off topic – PCs for running FPGA tools 34115: 01/08/14: Re: virtex2 Block Ram: dual port ram with different da 34221: 01/08/16: Re: Virtex-II and 5V devices 34223: 01/08/16: Re: Slowing PCI for FPGA 34224: 01/08/16: Re: Slowing PCI for FPGA 34225: 01/08/16: Re: Building a clock out of a PLD 34367: 01/08/22: Re: FPGA MP3 decoder 34399: 01/08/23: Re: Optical Bay Area Start-up! SW/HW Engs needed 34441: 01/08/24: Re: Principles of Verifiable RTL Design (2nd ed) 34442: 01/08/24: Re: Optical Bay Area Start-up! SW/HW Engs needed 34443: 01/08/24: Re: Reading Text in Verilog 34481: 01/08/27: Re: DRAM burst mode 34609: 01/08/30: Re: Defending Austin Franklin 34630: 01/08/31: Re: Ugly signal output…