Isn hardware generated by Rapid HDL sub-optimal?
Not necessarily. Rapid HDL scripts the output of Verilog. If the scripted output is a bad design, then the hardware will be slow. But there is no reason why the scripted output has to be a bad design if you have the time to do it right. If you don’t have the time to do it right, then Rapid HDL will help you do it faster, anyway. Your contrived FAQ questions didn’t answer my question Sorry. Please post your questions to the discussion board or the comments section.