ISE 8.2sp3 clobbering source file timestamps?
116566: 07/03/12: Re: odd warning in Xilinx ISE webpack 117946: 07/04/13: Re: SETUP & HOLD time confusion 119765: 07/05/25: Re: Use BRAM as ROM (Xilinx) 119947: 07/05/29: Re: Use BRAM as ROM (Xilinx) 119973: 07/05/30: Re: Use BRAM as ROM (Xilinx) 120011: 07/05/30: Re: LVDS termination scheme to nonstandard ribbon cable 120025: 07/05/31: Re: LVDS termination scheme to nonstandard ribbon cable 120046: 07/05/31: Re: LVDS termination scheme to nonstandard ribbon cable 120076: 07/05/31: Re: LVDS termination scheme to nonstandard ribbon cable 120081: 07/05/31: Re: LVDS termination scheme to nonstandard ribbon cable 120240: 07/06/04: Re: 180 differential inputs each 800Mbps using V5 120256: 07/06/04: Re: 180 differential inputs each 800Mbps using V5 120360: 07/06/05: Re: Virtex4 CLKX2 DCM Jitter 120570: 07/06/10: Re: LVPECL output skew 120572: 07/06/10: Re: XST net splitting blocks placement 120573: 07/06/10: Re: Lattce SC Purspeed I/O 120574: 07/06/10: Re: Virtex4 CLKX2 DCM Jitter 120575