Is Virtex 4 supported by Jbits ?
132068: 08/05/12: Re: value of the weak pull up resistor on IOBs of Virtex5 132107: 08/05/13: Re: power supply noise margin 132142: 08/05/15: Re: Cyclone 3 on chip termination 132146: 08/05/15: Re: question about high speed serial links with clock forwarding 132180: 08/05/16: Re: Cyclone 3 margins: none at all at 3.3v 132184: 08/05/16: Re: Resetting FPGA Without watch dog timer 132189: 08/05/16: Re: frame format virtex 5 132196: 08/05/16: Re: Cyclone 3 margins: none at all at 3.3v 132242: 08/05/19: Re: Resetting FPGA Without watch dog timer 132243: 08/05/19: Re: frame format virtex 5 132253: 08/05/19: Announcing Virtex 57! 132280: 08/05/20: Re: Stratix IV Announced 132316: 08/05/21: Re: Every newbie’s favorite project: the Quadrature Rotary Encoder 132343: 08/05/22: Re: 1250gbps input on virtex-5 132452: 08/05/27: ‘Nother one bites the dust 132453: 08/05/27: Re: ‘Nother one bites the dust 132694: 08/06/05: Re: Xilinx cuts 250 jobs.