Is there any performance advantage to having TX and RX FIFO size of greater than the 2K bytes, which is what is used by the current STE10/100A?
The STE10/100A does indeed support multicast address filtering. It does so through a hashing mechanism like that used by the 2114x family of devices. For Multicast filtering, the MM bit (bit 7) in CSR6 should be set to 0 (Note: Setting MM=1 (bit 7 in CSR6) will cause the STE10/100A to receive all Multicast packets regardless of the value in CSR27 & CSR28). Setting a value other than 0 in CSR27 and/or CSR28 allows the device to receive incoming frames with a multicast destination address (first bit in the destination address field is 1). Incoming frames with multicast destination addresses are subjected to imperfect filtering. Frames with physical destination addresses are checked against the single physical address in CSR25 & CSR 26. CSR26 and CSR27 are used to contain the 64-bit hash table used for imperfect multicast address filtering. Bit 10 of Receive Descriptor RDES0 is used to indicate that the received frame has a multicast address.
