Is there an advantage to running a higher VCO frequency than the output frequency?
Yes. As a clock input signal traverses the switching region of an input stage, random noise in the input stage adds time jitter to the signal as it is passed along to subsequent stages. A signal which traverses this switching region faster (has higher slew rate) is less affected by the random noise, resulting in less added time jitter, and lower jitter at the clock outputs. For a signal of the same amplitude, a higher frequency signal has a higher (faster) slew rate, and therefore can result in lower time jitter through the clock distribution system.
