Is the SCTL more real estate-efficient with FPGA resources?
Yes. Because your logic is implemented combinatorially in hardware, the FPGA configuration generated by the code uses less resources. Instead of doing an add, saving the result, and then a multiply and saving the result, the SCTL does both in one tick and does not have to save the result in between. This conserves FPGA resources because no flip flop is needed between operations to save the result of each previous operation.
