Is schematic entry supported?
The Design Entry and Synthesis module contains a graphical HDL design entry tool. This may be used to create and connect HDL blocks together to form a top level schematic. WebPACK ISE’s primary focus is HDL entry, design and synthesis. Should a user desire to create a schematic design using logic primitives, CPLD logic libraries are available as a backPACK module. Third party schematic designs are supported using WebPACK’s EDIF netlist entry. Foundation designs (both schematic and mixed schematic/HDL) which target the 9500 library are supported. Foundation users targeting the XC9500 should complete the implementation in Foundation. Foundation users targeting the XCR series must create an EDIF netlist file in Foundation and import the EDIF net list file into WebPACK.
