Is it possible that a Virtex II device performs below its spec?
66273: 04/02/16: Re: using fpga for sampling audio 66382: 04/02/18: Re: GZIP algorithm in FPGA 66634: 04/02/24: Re: SHARC 21062/21060 link port implementation on Virtex 2 FPGA 66658: 04/02/24: Re: Driving INOUT signals 66688: 04/02/25: Re: Driving INOUT signals 66694: 04/02/25: Re: Driving INOUT signals 66727: 04/02/25: Re: Modular Design in WebPack 66760: 04/02/26: Re: VHDL FSM Problem 66944: 04/03/01: Re: Driving INOUT signals 68702: 04/04/14: Re: Help – DDS Control in Virtex II 69049