IrDA controller macro: is it easy to design?
Karim LIMAM:15334: 99/03/19: Re: Xilinx Vhdl “‘event” synthesis problem16774: 99/06/08: Sensitivity list assumed to be complete17118: 99/07/01: Altera 10K prices17208: 99/07/09: Re: Altera 10K prices28989: 01/02/01: JTAG Programming with SpartanII demo card29022: 01/02/02: Re: JTAG Programming with SpartanII demo cardKarl:46392: 02/08/27: Re: Altera Quartus II problems47507