In synchronous chip design, designers commonly use Phase Locked Loops to deal with asynchrony across multiple voltage and clock domains. How is Elastix different from this?
PLLs are used to generate reliable clocks with very small jitter. If two different clock domains receive their clock from the same source (PLL), the clocks will run at the same frequency or at frequencies that are divided from the main frequency. In these conditions, synchronization between clock domains is a problem that can be solved by adjusting delays and reaching timing convergence. PLLs do not deal with asynchrony, they simply avoid asynchrony. A major problem with this approach is timing convergence for those systems that have many components, since the adjustment of delays is very complicated when several iterations are required to obtain a physical layout that meets all timing constraints. Moreover, different blocks may have different clock frequencies required to satisfy their performance constraints (e.g. interfacing to 100Mpbs Ethernet or decoding video at 30fps), which may be difficult to reduce the rational multiples of some base frequency. When using Elastic Clocks, ther
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