If multi A/D channels are used for sampling, then what points are there to note when using the A/D related registers?
Answer If multi A/D channels are used to implement sampling, then the first thing to note is the A/D clock source, which is controlled by the ADCS1 and ADCS0 bits. Because the minimum clock period tAD is specified at 1us, for this reason a suitable system clock division ration should be chosen using ADSC1 and ADSC0 according to what system clock speed is used to prevent the A/D clock period from being less than 1us and generating an inaccurate A/D conversion value. If more than one channel is selected for sampling, then it must be noted that only one conversion can be implemented each time, and by using the ADCR register bits ACS2~ACS0, the A/D channel that is connected to the internal A/D converter can be chosen. Finally the ADCR bits, PCR2~PCR0 are used to define which pins on the PB port are used as A/D converter inputs, and which pins are used as normal I/O pins. One point to note is that if any pins above PB0 are setup as A/D inputs, then all pins between that pin and PB0 will als
