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I try to debug the VHDL code in problem 1, but I keep getting “ieee_std_logic_1164.ALL not found” error. What could be wrong?

April 26, 2017code debug Error problem Try vhdl wrong

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I try to debug the VHDL code in problem 1, but I keep getting “ieee_std_logic_1164.ALL not found” error. What could be wrong?

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Problem 1 in the first assignment has a lot of syntax errors. You need to find them out. This is to get you familiar with the VHDL syntax. The library is there, but the syntax is wrong. So SYNOPSYS can’t find it.