How to resolve the IBQ stalls?
IBQ stalls are produced by the fetch pipeline and most of the time they are related to PC discontinuities. They can be encountered with BLOCKREPEAT, BRANCH, and CALL Instructions. This application report for TMS320C55x DSP SPRA865 shows how to resolve the IBQ stalls and align the target address (loop starting address) on a 32-bit boundary by adding nop instructions before the beginning of the loop. In order to optimize assembly code with respect to pipeline stalls, the DSP programmer needs to determine where the stalls occur, what the origin of the stalls is, and how, if possible, to remove the stalls.
