How to do system simulation?
module top (clk, reset_b, …); mltring processor(.clk(clk), .reset_b(reset_b), … ); memory left_right_bank(.address({la,ra}), .data({ld,rd}), … ); end; 5.3.7 – Post-synthesis simulation The idea is similar to how to do system simulation except the mltring module must come from the Verilog output generated by FPGA Express. 5.3.8 – Post-implementation (timing) simulation Again, the idea is exactly the same as post-synthesis except the mltring module must be from the “timesim.vhd” generated by Design Manager. You must apply the timesim.SDF at the right REGION: top/processor. I believe you applied to the top module instead. That can cause these many error messages. 5.3.9 – Issues to be concerned while using a memory model ($readmemh) The text file that contains the data must be in the “current directory” of ModelSim.
