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How to determine macro size in Xilinx Foundation?

April 26, 2017determine foundation macro size Xilinx

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How to determine macro size in Xilinx Foundation?

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13068: 98/11/14: Re: placement&routing problems 13071: 98/11/14: Re: placement&routing problems 13072: 98/11/14: Re: placement&routing problems 13711: 98/12/19: Re: Async Fifo Core or Macro for Xilinx FPGA 13716: 98/12/20: Re: Async Fifo Core or Macro for Xilinx FPGA 13998: 99/01/06: Re: Gamma correction in YUV space 14599: 99/02/06: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity) 14619: 99/02/06: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity) 14616: 99/02/06: Re: Synplify/Xilinx4085XLA question 16447: 99/05/22: IOB tristate register in Xilinx XLA devices 17036: 99/06/26: Major Exemplar Bug 17948: 99/09/18: Loadable arithmetic in Virtex 17951: 99/09/18: Virtex global set/reset 17955: 99/09/19: Re: Virtex global set/reset 17956: 99/09/19: Re: Loadable arithmetic in Virtex 17964: 99/09/19: Re: Loadable arithmetic in Virtex 18408: 99/10/23: Re: External Cloking of Altera MAX 7000S 35114: 01/09/21: Re: Virtex Clock Enable and Synplify 38663: 02/01/21: Re: D