How much would a PCI core be worth?
25755: 00/09/19: Re: Virtex-E: LVDS vs LVPECL26514: 00/10/18: Re: source PROM 1751226516: 00/10/18: Re: source PROM 1751226543: 00/10/19: CoolRunner news :(26576: 00/10/20: Re: CoolRunner news :(26583: 00/10/20: Re: CoolRunner news :(29034: 01/02/02: Re: Xilinx question29924: 01/03/18: Re: Senior I/O Designer – Canada30963: 01/05/04: Re: Reading FPGA output on Parallel Port35665: 01/10/12: Re: future Xilinx products wish list …35844: 01/10/19: Re: Glitch Hunting, a true story ;-)37014: 01/11/28: Re: Creating a jitter free clock38987: 02/01/29: Re: Books on DSP38996: 02/01/29: Re: Books on DSP39000: 02/01/29: Re: Memory Question on Virtex39048: 02/01/30: Re: Memory Question on Virtex40412: 02/03/06: Re: FPGA which supports LVDS44142: 02/06/12: Re: LVPECL open-emitter interface to Virtex-II46117: 02/08/19: Re: Polyphase filtering…47140: 02/09/18: Re: using CPLD’s inverter in oscillator circuit48294: 02/10/15: Re: VHDL v. Verilog, Xilinx v. Altera.