How is DRAM refresh performed during Suspend mode?
At the onset of suspend mode, the MTXC samples the SUS_STAT# pin active. This indicates to the north bridge that PCLK and HCLK will become invalid in as little as 32us. However, to maintain data integrity in the DRAM, refresh must continue. Thus, the MTXC is forced to use an alternate clock source (SUSCLK) for refresh timings. When the system resumes (comes out of power management), the HCLK will start. After reset, software sets the NREF (Normal Refresh Enable) bit in the MCTL register, switching the MTXC from suspend refresh to normal refresh (SUSCLK to HCLK). The entire MTXC, however, does not come out of suspend until SUS_STAT is de-asserted.
