How does the SGI Spider chip enable Craylink to function without contention and without running into an N-squared increase in system cost and complexity?
The Spider chip itself is non-blocking. Since each of its 6 ports supports 4 virtual channels there can be contention in that a packet with a recent age may wait while the on-chip arbiter enables an older packet to progress though the crossbar. This is a design decision and alternatives are being explored with the next version of the Spider chip which will also offer an increased number of ports (exact increase not yet disclosed). The fact that to create a totally non-blocking NxN switch requires on the order of N squared Spider chips is not relevant to the design of the SGI Origin as it does not use this architecture – it employs a variant of a hypercube. The cost of the system does scale close to linearly with a single discontinuity when expanding from 64 to 128 processors, then the number of Spider chips required resumes a linear increase. In terms of backplane connections between Spider chips these too increase in a direct linear relationship to the number of processors. Only the n
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