How does the LabVIEW compiler translate my graphical code into FPGA circuitry?
The LabVIEW FPGA module compiles your LabVIEW application to FPGA hardware using an automatic multistep process. Behind the scenes, your graphical code is translated to text-based VHDL code. Then industry standard Xilinx ISE compiler tools are invoked and the VHDL code is optimized, reduced, and synthesized into a hardware circuit realization of your LabVIEW design. This process also applies timing constraints to the design and tries to achieve an efficient use of FPGA resources (sometimes called “fabric”). A great deal of optimization is performed during the FPGA compilation process to reduce digital logic and create an optimal implementation of the LabVIEW application. Then the design is synthesized into a highly optimized silicon implementation that provides true parallel processing capabilities with the performance and reliability of dedicated hardware. The end result is a bit stream file that contains the gate array configuration information. When you run the application, the bit
