How does the DCM phase shifting circuitry work?
100372: 06/04/07: Re: LVDS in Cyclone-II (or in Spartan-3E) 100465: 06/04/10: Re: LVDS in Cyclone-II (or in Spartan-3E) 100633: 06/04/13: Re: Did National cheat with the Virtex 4 100725: 06/04/17: Re: Did National cheat with the Virtex 4 100758: 06/04/17: Re: Did National cheat with the Virtex 4 100928: 06/04/21: Re: Editing Spartan3 DCM in FPGA(8.1.03) editor 100939: 06/04/21: Re: Editing Spartan3 DCM in FPGA(8.1.03) editor 102611: 06/05/17: Update: Simple ADS5273 -> Xilinx Interconnect Model 102842: 06/05/22: Re: [Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins 102862: 06/05/22: Re: [Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins 102983: 06/05/24: Re: ISE 8.1SP4 PN doesnt start 103336: 06/05/31: Re: Need help reattaching top to FPGA 103922: 06/06/14: open inputs and Unisim libraries 103957: 06/06/15: Re: Virtex2-Pro local clocking… 106191: 06/08/08: Re: Spartan 3 StarterKit Weirdness 106435: 06/08/13: Re: Embedded clocks 106538: 06/08/14: Re: Embedded clocks 108753