How Does Sample-Clock Jitter Relate to Interface Jitter Measured at the AES/EBU or SMPTE Output Connectors?
Sample clock jitter cannot be measured at an AES/EBU or SMPTE output connector. The reason is simple: AES interface standards require bandwidth and rise-time limiting in order to reduce electromagnetic interference. As a result, the AES interface will add code-dependent jitter, which may be 100 to 1000 times greater than the jitter at the converter’s sample and hold. This is potentially inconsequential. This interface jitter accumulates after the audio is in the digital domain, and therefore, does not degrade the audio signal, provided it is removed prior to D-to-A conversion. But, unlike interface jitter, sample clock jitter cannot be removed. Therefore it is critical to measure the sample clock jitter by itself.
