How does OpenVera relate to SystemC?
A10. OpenVera is a specially tuned verification language for use by designers and verification engineers developing testbenches for hardware validation, typically as part of a Verilog or VHDL flow. OpenVera includes a broad range of constructs that enable constraint driven random test stimulus generation, real time self-checking, functional coverage, and temporal assertions. The Vera language is in use for functional verification for the last 5 years at over 100 customer sites. SystemC is the modeling language for use by system designers, SW engineers and HW engineers developing system level models for analysis in a C based flow. Both languages are used by customers for respective uses. Synopsys will continue to support both.
