How does Low Voltage Differential Signaling (LVDS) compare to other differential interface standards?
LVDS is a current loop signaling technology in which the current loop direction (clockwise or counter-clockwise) determines the logic level (high or low). Approximately 3.5mA is driven down one wire of the pair and returns through the other wire of the pair. A voltage (approx. +/-3.5mA x 100Ω = +/-350mV) is generated across the termination resistor. The receiver, a differential comparator, measures the polarity of this voltage drop, positive voltage corresponding to logic high and negative voltage to logic low. LVDS provides the smallest swing of 350mV and a robust common-mode range of +/-1V around its offset voltage (VOS). Some devices are specified to have a common mode range that meets or in some cases exceeds the supply voltage. LVDS is primarily used for point-to-point or multidrop applications with certain flavors like Bus LVDS (BLVDS) and Multipoint LVDS (MLVDS) supporting multipoint configurations. Due to the output current and edge rates, LVDS is targeted for the DC to 2Gbps r
