How does EPC handle the “Miller Effect”?
“Miller Capacitance”, CGD, is quite low for these devices. Therefore, switching losses due to the “Miller Effect” are quite low. Handling the “Miller Effect” during a dV/dt is similar to handling it in MOSFETs. In low voltage devices, the capacitive divider between CGD and CGS is enough to keep the device off. At higher voltages, a low impedance turn off path is required to keep a device off under dV/dt. The challenge in handling this is that negative VGS is added to the VF and may cause “body diode” losses to increase. Care must be taken in evaluating this trade-off.
