How Does a Pipeline ADC Work?
The pipelined ADC has become the most popular ADC architecture for sampling rates from a few Msps up to more than 250Msps. Resolution is in the range of 8 bits at the faster sampling rates, up to 16 bits at the lower sampling rates. In this architecture, the converter is multistage and accepts a signal before completing the conversation of the previous signal. In this method, one stage processes data received from the previous stage during a clock cycle. At the end of the clock cycle, the output of a given stage is passed to the next stage using T/H and new data is fed to the previous stage. Examples of pipeline converters are the dual-channel MAX19515 (10-bit, 65Msps), MAX19516 (10-bit, 100Msps), and MAX19517 (10-bit, 130Msps). The MAX19586 is a high-dynamic-range, 16-bit, 80Msps ADC with -82dBFS noise floor. At 100Msps, the MAX19588 offers an industry-leading -82dBFS noise floor for a new generation of high-sensitivity equipment. Maxim also offers a pin-compatible family of 170Msps t
