How does a digital design flow fit into L-Edit?
Below is a description of what is involved in doing a digital design in VHDL/Verilog and where it fits into L-Edit. • Design in Verilog/VHDL. • Simulate in a digital simulator such as Mentor’s ModelSim. • Synthesize your VHDL/Verilog netlist with a synthesis tool such as Mentor’s Leonardo Spectrum. You will need to provide Leonardo a synthesis library which basically is a mapping table for your layout standard cell library. This is pretty much the same way as you would provide Leonardo with a Xilinx part library so that it can map your circuit to the LUTs in an FPGA. • The output of the synthesis will be an EDIF file which can then be into L-Edit’s SPR (Standard Place and Route) along with a layout standard cell library file to be placed and routed. • The timing delay information of the placed and routed chip can be obtained by exporting a SDF (Standard Delay Format) file. In order to obtain this file, a liberty file (.lib) is required to import into L-Edit to establish the timing char
