How do the embedded clock receivers continue to recover a RCLK when I stop sending data on the transmitter side?
Once the transmitter PLL is locked to the TCLK, it continues to send a clock bit. If no data is present at the TTL inputs, these pins have internal pull-downs that will provide an all 0 data pattern (with the exception of the start bit) at the LVDS outputs. Customers can use the DEN pin to disable the LVDS outputs, but the LVDS receiver will need to relock to the incoming data stream.
Related Questions
- For transmitters and receivers with an embedded clock, why does a recovered clock (RCLK) signal appear after data is no longer being sent to the transmitter inputs?
- Can the foreign signatories continue to exchange amongst themselves controlled data that they have received under a TAA, after this TAA has expired?
- How do simultaneous data and clock signal jitter prevent readability?
